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HANBit
HSD16M32F4VP
Synchronous DRAM Module, 64Mbyte ( 16M x 32-Bit ) SMM based on 2Mx16Bitx4Banks, 4K Ref., 3.3V Part No. HSD16M32F4VP
GENERAL DESCRIPTION
The HSD16M32F4VP is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 2M x 16 bit with 4banks Synchronous DRAMs in TSOP-II packages is mounted on a 80-pin, single-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M32F4VP is a SMM (Stackable Memory Module) designed and is intended for mounting into two 40pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification
HSD16M32F4VP-10L * Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * 80pin-SMM type FR4-PCB design * The used device is 2Mx16Bitx4Bankst SDRAM * Pin assignment is compatible with - HSD8M32F4VP - HSD16M32F4VP - HSD32M32F4VP 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC Vss NC CKE0 /CS0 /CS1 NC NC Vss /WE DQM0 DQM1 DQM2 DQM3 Vcc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1 2 3 4 5 Symbol Vcc /RAS /CAS NC CLKA PIN 21 22 23 24 25
PIN ASSIGNMENT
40-PIN P1 Connector Symbol Vcc DQ0 DQ1 DQ2 DQ3 DQ4 Vss DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 Vss DQ11 DQ12 DQ13 DQ14 DQ15 Vcc PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-PIN P2 Connector Symbol Vcc DQ31 DQ30 DQ29 DQ28 DQ27 Vss DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 Vss DQ20 DQ19 DQ18 DQ17 DQ16 Vcc PIN 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol Vcc BA0 BA1 NC NC A11 Vss A10 A9 A8 A7 A6 A5 Vss A4 A3 A2 A1 A0 Vcc
Stackable Memory Module TOP VIEW
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FUNCTIONAL BLOCK DIAGRAM
HSD16M32F4VP
DQ0-31
CKE0 /CA
/RAS S
/CS0
CKE CAS 15 RAS CE CKE CAS RAS CE CKE CAS RAS WE WE
U1
CLK DQ0LDQM UDQ BA0-1 M CLK DQ16-31 LDQM UDQ BA0-1 M CLK DQ0-15 LDQM UDQM BA0-1
CLKA DQM0 DQM1
A0-A11
U2
A0-A11
DQM2 DQM 3
U3
WE A0-A11
DQM0 DQM 1
/CS 1
CE
CKE CAS RAS CE WE
U4
A0-A11
/WE A0 - A11 BA0-1
CLK DQ16-31 LDQ UDQ BA0-1 M M
DQM2 DQM3
Vcc Vss
Two 0.1uF Capacitors per each SDRAM
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PIN FUNCTION DESCRIPTION
Pin CLK /CS Name System clock Chip select Input Function
HSD16M32F4VP
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.
/CAS
Column strobe
address
Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~3
Data mask
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
DQ0 ~ 31 VCC/VSS
Data input/output Power supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1V to 4.6V -1V to 4.6V 4W -55oC to 150oC
Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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HSD16M32F4VP
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE
Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23 C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Clock /RAS, /CAS,/WE,/CS, CKE, DQM Address DQ (DQ0 ~ DQ7) SYMBOL CCLK CIN CADD COUT MIN 2.5 2.5 2.5 4.0 MAX 4.0 5.0 5.0 6.5 UNITS pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current ICC1 (One bank active) tRC tRC(min) IO = 0mA Precharge current in power-down mode ICC2PS standby ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= Precharge current in non power-down mode one time during 20ns standby ICC2N CKE VIH(min) CS* VIH(min), tCC=10ns Input signals are changed 80 mA 4 mA 4 mA 300 mA 1 HSD16M32F4VP-10L UNIT E NOT
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CKE VIH(min) ICC2NS CLK VIL(max), tCC= Input signals are stable ICC3P Active standby current in power-down mode ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), CS*VIH(min), tCC=10ns ICC3N Active standby current in non power-down mode (One bank active) ICC3NS Input signals are changed one time during 20ns CKEVIH(min) CLK VIL(max), tCC= Input signals are stable IO = 0 mA Operating current ICC4 (Burst mode) 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC tRC(min) CKE 0.2V 840 1.5 Page burst 350 80 120 20 28
HSD16M32F4VP
mA 20
mA
mA
1
mA mA
2
Self refresh current ICC6 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70 C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V
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+3.3V
HSD16M32F4VP
Vtt=1.4V
1200 DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load circuit DOUT Z0=50
50 50pF
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data SYMBOL tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
HSD16M32F4VP-10L 20 20 20 50 100 70 2 2 CLK + 20 ns 1 1 1 2
UNIT ns ns ns ns ns ns CLK CLK CLK CLK ea
NOTE 1 1 1 1
1 2
tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3
2 2 3 4
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
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AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) HSD16M34F4VP-10L PARAMETER CLK cycle time CAS tCC latency=3 CLK to valid output delay Output data hold time CAS tSAC latency=3 CAS tOH latency=3 tCH tCL tSS tSH tSLZ tSHZ in Hi-Z latency=3 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. 3 3 2 1 1 6 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output CAS 3 6 10 1000 SYMBOL MIN MAX
HSD16M32F4VP
UNIT
NOTE
ns
1
ns
1,2
ns ns ns ns ns ns ns
2 3 3 3 3 3 2
SIMPLIFIED TRUTH TABLE
CKE n-1 H H L H CKE n X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1 A10/ AP OP code X X Row address L H X L H L H X V H Column Address (A0 ~ A8) Column L H precharge H X L L H L X X L H L L X V H X
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COMMAND Register Mode register set Auto refresh Refresh Self refres h Auto disable Auto disable Auto disable Auto disable Burst Stop
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A11 A9~A0
NOTE 1,2 3 3 3 3
Entry Exit
Bank active & row addr. Read & column address precharge precharge
4 4,5
Write & column address
precharge
Address (A0 ~ A8)
4
4,5 6
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Precharg e Bank selection All banks Entry Exit Entry Exit H H L H L H H X H L X L H L H L H L X H L H L L X V X X H X V X X H X H X H H X V X X H X V L X V X X H X V X X X X V X
HSD16M32F4VP
L H X X
Clock suspend or active power down
Precharge down mode DQM
power
X X V X X X 7
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
PACKAGING INFORMATION
Unit : mm
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HSD16M32F4VP
HSD16M32F4VP
Connector Configuration
- Module PCB Bottom: AXN440530, 0.8mm Free Height Plugs,40pins - Board top, Module PCB Top: AXN340130 ,0.8mm Free Height Receptacles , 40pins
ORDERING INFORMATION
Part Number Density Org. Package 80 Pin SMM Ref. Vcc Interface MAX.frq 100MHz (CL=3)
HSD16M32F4VP-10L
64MByte
16Mx 32
4K
3.3V
LVTTL
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